1. Field of the Invention
The present invention relates to a scan electrode driving circuit and a display apparatus having the scan electrode driving circuit.
2. Description of the Related Art
A display apparatus such as a liquid crystal display apparatus or the like has a display panel and a peripheral unit. The peripheral unit is connected to the display panel and controls the display panel. The display panel has a plurality of scan electrodes, a plurality of data electrodes and a plurality of pixel cells. The plurality of scan electrodes are perpendicular to the plurality of data electrodes, and the plurality of pixel cells are provided at regions where the plurality of scan electrodes cross the plurality of data electrodes. The peripheral unit has a scan electrode driving circuit and a data electrode driving circuit. The scan electrode driving circuit applies a scanning signal to the plurality of scan electrodes in order. A scan electrode to which the scanning signal is applied is a selected scan electrode, and pixel cells connected to the selected scan electrode are selected pixel cells. Also, the data electrode driving circuit applies to the plurality of data electrodes pixel voltages which are associated with image data. Thus, the pixel voltages are supplied to the selected pixel cells and the image data is displayed on the display panel.
The scan electrode driving circuit has shift registers, level shift circuits and output buffers. The shift registers generate scanning signals. Each level shift circuit converts voltage level of the scanning signal from low voltage level to high voltage level. Here, a signal with high voltage level is used in the display panel. Each output buffer supplies the scanning signal with high voltage level to a scan electrode. The circuit scale of the scan electrode driving circuit is dependent on the number of the plurality of scan electrodes in the display panel.
As shown in FIG. 1, for example, such a conventional display apparatus has an LCD (Liquid Crystal Display) panel 1, a data electrode driving circuit 2, a scan electrode driving circuit 3 and a timing controller 4. The LCD panel 1 has data electrodes Xi (i=1, 2 to m, for example, m=640×3), scan electrodes Yj (j=1, 2 to n, for example, n=512) and pixel cells 10i,j. Pixel voltages Di are applied to the data electrodes Xi. Scanning signals OUTj are applied to the scan electrodes Yj in order. The pixel cells 10i,j are provided at regions where the data electrodes Xi cross the scan electrodes Yj. Each pixel cell 10i,j has a TFT (Thin Film Transistor) 11i,j, liquid crystal cell 12i,j and a common electrode COM. Based on image data VD received from a control unit (not shown), the data electrode driving circuit 2 applies the pixel voltages Di to the respective data electrodes Xi. The scan electrode driving circuit 3 has two driving circuit blocks 31, 32, for example. This scan electrode driving circuit 3 applies the scanning signals OUTj to the respective scan electrodes Yj in order. The timing controller 4 outputs a control signal Sf to the data electrode driving circuit 2, and controls the operation of the data electrode driving circuit 2. Also, the timing controller 4 outputs an initiation signal Sg to the scan electrode driving circuit 3, and controls the operation of the scan electrode driving circuit 3.
FIG. 2 is a circuit diagram showing a configuration of the driving circuit block 31 in FIG. 1. As shown in FIG. 2, this driving circuit block 31 has shift registers 410, 411, 412 and 413, output level shift circuits 420, 421, 422 and 423, and output buffer circuits 430, 431, 432 and 433. In response to an initiation signal Sg, the shift register 410 outputs scanning signals Se1, Se2 to Se64 in order in synchronization with a clock signal (not shown). Also, the shift register 410 outputs an initiation signal Sg0 together with the scanning signal Se64. In response to the initiation signal Sg0, the shift register 411 outputs scanning signals Se65, Se66 to Se128 in order in synchronization with the clock signal. Also, the shift register 411 outputs an initiation signal Sg1 together with the scanning signal Se128. In response to the initiation signal Sg1, the shift register 412 outputs scanning signals Se129, Se130 to Se192 in order in synchronization with the clock signal. Also, the shift register 412 outputs an initiation signal Sg2 together with the scanning signal Se192. In response to the initiation signal Sg2, the shift register 413 outputs scanning signals Se193, Se194 to Se256 in order in synchronization with the clock signal. Also, the shift register 413 outputs an initiation signal Sg3 together with the scanning signal Se256.
The output level shift circuits 420, 421, 422 and 423 convert voltage level of the scanning signals Se1 to Se64, Se65 to Se128, Se129 to Se192 and Se193 to Se256 from the low voltage level to the high voltage level, respectively. The output buffer circuits 430, 431, 432 and 433 output the converted scanning signals Se1 to Se64, Se65 to Se128, Se129 to Se192 and Se193 to Se256 as scanning signals OUT1 to OUT64, OUT65 to OUT128, OUT129 to OUT192 and OUT193 to OUT256, respectively. The outputted scanning signals OUT1 to OUT256 with high voltage level are applied to the scan electrodes Y1 to Y256, respectively.
The driving circuit block 32 is configured similarly to the driving circuit block 31, and cascade-connected to the driving circuit block 31. In response to the initiation signal Sg3 outputted from the driving circuit block 31, the driving circuit block 32 applies scanning signals OUT257 to OUT512 with high voltage to the scan electrodes Y257 to Y512 in synchronization with the clock signal, respectively.
In this conventional LCD apparatus, the scan electrode driving circuit 3 applies the scanning signals OUTj to the scan electrodes Yj (j=1˜512) in order, respectively. Thus the pixel cells 10i connected to the selected electrode Yj are selected. Also, the data electrode driving circuit 2 applies the pixel voltages Di to the data electrodes Xi. Thus, the pixel voltages Di are supplied to the selected pixel cells 10i, and hence the image data VD is displayed on the LCD panel 1.
However, there are the following problems with this conventional LCD apparatus shown in FIG. 1.
That is to say, it is necessary to prepare a lot of shift registers, output level shift circuits and output buffer circuits in the scan electrode driving circuit 3 according to the number of the scan electrodes Yj (j=1 to 512), as shown in FIG. 2. Thus the circuit scale of the scan electrode driving circuit 3 becomes large. In particular, when this scan electrode driving circuit 3 is formed in a rectangular chip, it is difficult to reduce the length of the short side of the rectangular chip. The peripheral unit surrounding the LCD panel 1, in which the scan electrode driving circuit 3 is provided, is associated with a marginal area of this LCD apparatus. Therefore, it is difficult to make the marginal area of the LCD apparatus narrower. Moreover, the larger the circuit scale of the scan electrode driving circuit 3 becomes, the more cost are required and the more complex it becomes to manufacture the LCD apparatus.
Also, Japanese Laid Open Patent Application (JP-P2002-278494A) discloses another LCD apparatus. FIG. 3 schematically shows a configuration of a scan electrode driving circuit of the LCD apparatus in the patent document.
In the scan electrode driving circuit, outputs from shift registers SR61˜SR116 can be supplied to the corresponding scan electrodes in two ways. That is, two switch circuits are connected to each of the shift registers SR61˜SR116. More specifically, switching circuits SW1˜SW56 and switching circuits SW116˜SW61 are connected to the shift registers SR116˜SR61 through decoders DE116˜DE61. A control signal SEL_UP activates the switching circuits SW1˜SW56. A control signal SEL_LO activates the switching circuits SW61˜SW116. At first, a driving signal is shifted from the shift register SR116 to the shift register SR61 in order. After that, the driving signal is shifted from the shift register SR61 to SR57, SR58, SR59, SR60. Then, a control signal SEL_SFT is inputted, which reverses the direction of the signal shifting in the shift registers SR61˜SR116. Thus, the driving signal is shifted from the shift register SR61 to the shift register SR116 in order. When a shift register SR receives the driving signal, the corresponding decoder DE generates a scanning signal, and outputs the scanning signal to the corresponding scan electrode through the activated switching circuit SW. According to this scan electrode driving circuit, the shift registers SR61˜SR116 and the decoders DE61˜DE116 are shared. Therefore, the number of circuits is reduced.
This scan electrode driving circuit is formed in a rectangular chip. Output pads connected to the switching circuits SW1˜SW56 are formed along one long side of the rectangular chip. On the other hand, output pads connected to the switching circuits SW61˜SW116 are formed along the other long side of the rectangular chip. Therefore, the configuration of wirings connecting the switching circuits SW and the output pads becomes complicated. Moreover, regions occupied by the wirings become large. Thus, similar to the above-mentioned conventional LCD apparatus, it is also difficult to make the peripheral unit smaller.
It is required to make the peripheral unit smaller and hence to make the marginal area narrower.